1. Field of the Invention
The invention relates generally to non-volatile semiconductor memory devices, and more particularly to a non-volatile semiconductor memory structure comprising a multi-trapping layer comprising a plurality of silicon-rich, silicon nitride charge-trapping layers.
2. Background of the Invention
Electrically erasable programmable read only memories (EEPROM) rely on charge injection and removal to establish a stored logic state. This is in contrast to conventional dynamic random access memory (DRAM), which requires periodic refresh pulses in order to maintain the logic state in a capacitive storage element. Conventional EEPROM devices generally comprise a field effect transistor (FET), wherein the gate electrode is formed over a portion of the silicon substrate between two diffusion regions. The diffusion regions act as the source and gate for the FET. The gate electrode in conventional EEPROM devices comprises some form of injection layer into which charges are injected from a channel induced in the silicon substrate below the gate electrode.
In practice, it is difficult to precisely control the extent of charge injection from the induced channel region. A silicon oxide layer separating the channel region from the injection layer must be thin enough to allow charge transfer and yet thick enough to allow the injection layer to retain and store the injected charge. These characteristics are very sensitive to changes in the thickness and/or stoichiometry of the oxide film.
In order to surmount these difficulties, researchers have attempted to construct EEPROM cells that do not rely upon charge injection from an induced channel region. One such device makes use of a non-conductive charge-trapping structure formed from silicon-rich, silicon nitride (Si3N4). The silicon-rich, silicon nitride-trapping layer of one such device is fabricated using LPCVD with different flow rate ratios (R) of dichlorosilane and ammonia.
Such a device provides a non-conductive charge-trapping structure that is not dependent on carrier injection in order to establish a stored logic state. Further, such a device provides a charge-trapping structure that is not overly sensitive to small variations and thickness and/or stoichiometry; however, a drawback to such device is that it only comprises a single trapping layer and therefore can only store a single logic state, orbit.